Effective Software-Based Self-Testing for CMOS VLSI Processors

Processor testing approaches based on the execution of self-test programs have been recently proposed as an effective alternative to classic external tester-based testing and pure hardware built-in self-test (BIST) approaches. Software-based self-testing is a non-intrusive testing approach that embeds a “software tester” in the form of a self-test program in the processor on-chip memory. It has the potential to provide high quality at-speed testing using low-cost external ATE without any hardware or performance overheads. In this thesis, we introduce a high-level, software-based self-testing methodology for embedded processors and microprocessors. The proposed methodology aims at high structural fault coverage with low test development and test application cost. We demonstrate the effectiveness and efficiency of the proposed methodology by completely applying it on several processor benchmarks with scaling complexity, implementing different implementations of a popular RISC instruction set architecture with several gatelevel implementations.